A configurable DRAM macro design for 2112 derivative organizations to be synthesized using a memory generator
Tomoaki Yabe, Satoru Miyano, K. Sato, M. Wada, Ryousuke HAGA, Osamu Wada, M. Enkaku, Takehiko Hojyo, K. Mimoto, Masaaki Tazawa, Tetsui Ohkubo, Kenji Numata · IEEE Journal of Solid-State Circuits · 1998
This paper describes a DRAM macro design from which 2112 configurations up to 32 Mb can be synthesized using a memory generator. The memory generator automatically creates the layout of a DRAM macro in accordance with specification inputs such as memory capacity, address count, bank count, and I/O bits count. An expandable floor layout scheme achieves the macro size comparable to that of handicraft-designed DRAM. The memory generator can customize a configurable redundancy scheme for various macro configurations. Unified testing circuits make it possible to test DRAM macros with more than 500 interface pins in a direct-memory-access mode with 33 test pads. Up to four macros on the same chip can be tested with them. Test chips with 4-Mb DRAM and with 20-Mb DRAM fabricated with 0.35-/spl mu/m technology showed 150-MHz operation.