A practical method for high-level synthesis of combinational logic from VHDL
G. Morton, R.L. Haggard · 2002
This paper demonstrates a method to allow rapid design from a high level VHDL program down to a simple netlist. Each stage of the design process generates a complete design representation as the behavioral axis of the Y-chart is descended. These design representations can be simulated to verify operation at each stage. The result is a fast and efficient method for digital design.>