A reconfigurable digital IC tester implemented using the ARM Integrator rapid prototyping system
Fang Pang, Tyler L. Brandon, B.F. Cockburn, M. Hume · 2004
We describe the implementation of a low-cost, highly-reconfigurable digital integrated circuit (IC) tester using the ARM Integrator ARM7TDMI/sup /spl reg//-based rapid prototyping system (RPS). The IC tester is controlled through a user interface application that runs on the RPS personal computer (PC) host. Test vectors and expected response vectors are developed off-line and then downloaded via the PC into the tester's pattern memory, which; is implemented in the RPS's SDRAM. The test vectors are then applied at up to 20 MHz to the inputs of the device under test (DUT) using no-return-to-zero (NRZ) formatting; meanwhile, the DUT output signals are sampled mid-cycle and the resulting actual response vectors are compared against stored-expected responses to determine if the DUT is functioning properly. A Xilinx Virtex-E field-programmable gate array (FPGA) in the RPS is used to implement the pipeline that demultiplexes and formats the test vectors, compares actual and expected response vectors, and collects failure statistics. The FPGA is also used to implement the expected response memory. When the test has finished, the actual responses and comparison results can be uploaded from the FPGA RAM to the PC and stored in a text file.