A monolithic digital chirp synthesizer chip with I and Q channels
Vernon E. Andrews, C.T.M. Chang, John Cayo, S. Sabin, William A. White, M. P. Harris · IEEE Journal of Solid-State Circuits · 1992
A monolithic digital chirp synthesizer (DCS) chip has been developed using GaAs/AlGaAs HI/sup 2/L technology. The 6500-HBT-gate DCS chip is capable of producing linear frequency-modulated (chirp) waveforms or single-frequency waveforms. The major components of the DCS are two 28-b pipelined accumulators, a 1.8 kb sine ROM, a 1.8 kb cosine ROM, and two 8 b digital-to-analog converters (DACs). The total chip area is 4.877 mm*6.172 mm using a minimum feature size of 1.5 mu m. All components of the DCS are fully functional and the device has been clocked to 450 MHz with a power dissipation of 18 W.>