A novel reprogrammable interconnect architecture with decoded RAM storage
R. Guo, Hung V. Nguyen, A. D. Srinivasan, Q. Nasir, Hong Cai, S.M.L. Law, A.M. Mohsen · 1994
Using a new architecture and routing scheme, a second generation 1024 pin interconnect device features up to 40% die size reduction and twice the speed. A novel decoded RAM storage and 5 T RAM cell yield the area reduction. The new architecture also adds 256 buffers. Unbuffered paths are passive and bi-directional. The programming time of on-chip memory also improves dramatically from 40 ms to less than 1 ms.>