A high-performance 1D-DCT architecture
A.M. Shams, Wendi Pan, A. Chandanandan, Magdy Bayoumi · 2002
A high performance 1D-DCT is proposed. It is based on a new distributed arithmetic architecture technique (NEDA). Only addition operations are used, with 35 additions to complete the first phase of the computations. The final phase is the primitive add-and-shift operation. No subtraction, multiplication, or ROM are needed. High-throughput is achieved by pipelining the architecture. The delay of one stage is the delay of one 12-bit addition. Low power consumption is achieved by reducing the computation requirements compared to other implementations of the 1D-DCT.