A HARDWARE IMPLEMENTATION OF THE APE100 ARCHITECTURE
Alessandro Bartoloni, G. Bastianello, C. Battista, Simone Cabasino, F. Marzano, Pier Stanislao Paolucci, J. Pech, F. Rapuano, Emanuele Panizzi, Renata Sarno, G.M. Todesco, Mario Torelli, WALTER TROSS, P. Vicini, N. Cabibbo, A. Fucci, R. Tripiccione · International Journal of Modern Physics C · 1993
APE100 processors are based on a simple Single Instruction Multiple Data architecture optimized for the simulation of Lattice Field Theories or other complex physical systems. This paper describes the hardware implementation of the first APE100 machine.