A DSP implementation of a voice transcoder for VoIP gateways
Armein Z. R. Langi · Asia Pacific Conference on Circuits and Systems · 2003
The objective of this research is to design and implement high-quality speech compression in real-time on a single-chip transcoder system. Based on voice over Internet protocol (VoIP) requirements, we have decided to implement multipulse maximum, likelihood quantization (MP-MLQ) and algebraic code excited linear prediction (ACELP) (used in an ITU-T G.723.1 standard) on a DSP processor TMS320C5402. The goal is to implement a high quality speech coding (with signal-to-noise ratio, SNR of more than 10 dB), at a low bit rate of 8 kbit/s or less. The coder must have a delay not more than 100 ms. Furthermore the resulting system must be shown to fit within a single chip. Using an ITU-T reference code, we use a series of iterative code optimization efforts. This rapid development approach is successful in achieving the requirements in a three man-month effort. The program requires 58-73 MIPS computation and 39 Kword memory, thus fits within the single chip of a 100 MIPS TMS320C5409. Total delay time is 59.4 ms. The bit rates are as low as 5.3 kbit/s and 6.3 kbit/s, with SNRs of 11.52 dB and 12.72 dB, respectively.