A 5 Gb/s 9-port application specific SRAM with built-in self test
Steven W. Wood, G.F.R. Gibson, Saman Adham, Benoit Nadeau-Dostie · 2002
Describes the architecture of a time-slot interchange (TSI) SRAM for a SONET switching application and its associated BIST architecture. To reduce the number of data RAMs required for full switching, the memory throughput is boosted by providing multiplexed access to the core at twice the system clock rate. The nature of the memory requires a novel BIST architecture to ensure full test coverage and ensure easy access of the BIST function at different levels of system integration.