Detection of Interconnect Open Faults with Unknown Values by Ramp Voltage Application
Yukiya Miura · Asian Test Symposium · 2006
We have proposed a method for detecting interconnect open faults of CMOS combinational circuits by applying a ramp voltage to the power supply terminal. The method can assign a known logic value to a fault location automatically by applying a ramp voltage and as a result, it requires only one test vector to detect a fault as a delay fault or an erroneous logic value at primary outputs. In this paper, we show fault detectability and effectiveness of the proposed method by simulation-based and theoretical analysis. We also expose that the method can be applicable to every fault location in a circuit and open faults with unknown value. Finally, we show ATPG results that are suitable to the proposed method.