Memory Hierarchy Targeting Bi-Predictive Motion Compensation for H.264/AVC Decoder
Bruno Zatt, Arnaldo Azevedo, Luciano Volcan Agostini, Altamiro Susin, Sérgio Bampi · 2007
This paper presents a motion compensation memory hierarchy for an H.264/AVC decoder with support to bi-predictive frames. The designed memory hierarchy reduces the memory bandwidth through the use of a three-dimensional cache and through the use of extra memory saving techniques. The cache size parameters were determined through the evaluation of simulation results from real video sequences. The designed memory hierarchy provides, in average, a 60% of bandwidth reduction. The architecture was designed in VHDL and synthesized for a Xilinx Virtex-II PRO FPGA