DVS: an object-oriented framework for distributed Verilog simulation
Lijun Li, Hai Huang, Carl Tropper · 2003
Abstract There is a wide-spread usage of hardware design lan-guages(HDL) to speed up the time-to-market for the design of modern digital systems. Verification engineers can sim-ulate hardware in order to verify its performance and correctness with help of an HDL. However, simulation can'tkeep pace with the growth in size and complexity of circuits and has become a bottleneck of the design process. Dis-tributed HDL simulation on a cluster of workstations has the potential to provide a cost-effective solution to this prob-lem. In this paper, we describe the design and implementa-tion of DVS, an object-oriented framework for distributed Verilog simulation. Verilog is an HDL which sees wide in-dustrial use. DVS is an outgrowth of Clustered Time Warp, originally developed for logic simulation. The design of theframework emphasizes simplicity and extensibility and aims to accommodate experiments involving partitioning and dy-namic load balancing. Preliminary results obtained by simulating a 16bit multiplier are presented. 1