Parallel form of the Pipelined Lifting-Based VLSI Architectures for Two-dimensional Discrete Wavelet Transform
Ibrahim Saeed Koko, Herman Agustiawan · International Journal of Computer Theory and Engineering · 2009
In this paper, in order to best meet real-time applications of 2-dimensional discrete wavelet transform (2-D DWT) with demanding requirements in terms of speed and throughput, 2-parallel and 4-parallel pipelined lifting-based VLSI architectures for lossless 5/3 and lossy 9/7 algorithms are proposed. The two proposed parallel architectures achieve speedup factors of 2 and 4 as compared with single pipelined architecture based on the first scan method proposed by Ibrahim et al. The advantage of the proposed parallel architectures is that the total temporary line buffer (TLB) does not increase from that of the single pipelined architecture proposed by Ibrahim et al. when degree of parallelism is increased.