A 120 MFLOPS CMOS floating-point processor
P. Chai, T. Chuk, Y.H. Fong, L. Hu, K. Ng, J. Prabhu, A. Quek, A. Samuels, Je-Kwang Yeun · 2002
A 60-MHz CMOS floating-point processor has been designed with 120 MFLOPS double-precision peak rating and a bus bandwidth of 1.44 GB/s. Using a novel floating-point algorithm, it performs floating-point add, multiply, divide, square-root, and inverses, and it supports parallel 64-bit load and store.>