Processor architecture driven algorithm optimization for fast 2D-DCT
I. Kuroda · 2002
This paper presents a fast two-dimensional (inverse) discrete cosine transform optimized for software implementation on a RISC microprocessor with an integer multiplier-accumulator (MAC) unit. The number of processor cycles as well as computational error is less than that of the row-column approaches based on fast 1D DCTs. The algorithm is implemented on a 100 MIPS 32-bit scalar RISC microprocessor V830 which has a MAC unit. The 8/spl times/8 DCT/IDCT for MPEG1 size (352/spl times/240) video with 30 frames/sec can be processed with 38.5 MIPS on V830.