Extended Sequential Logic for Synchronous Circuit Optimization and Its Applications
Pramod Kumar Meher · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2009
In this paper, we present a new approach for the extension of sequential logic functionality ofDflip-flop in order to perform an additional Boolean function simultaneously along with its usual bit-storage function. We show that a combinational function of the form (amiddotb), (a+b) , (a+[(b)]), or ([(a)] middotb) which occurs frequently in a feedforward path with aDflip-flop could be implemented efficiently by aDflip-flop with RESET or SET provision. Similarly, (aoplusb) or ((amiddotb) oplusc) in the feedback loop with aDflip-flop could be implemented by aTflip-flop by suitable modification of the clock. The use of such extended sequential logic is found to result in a significant reduction in critical path and saving in area complexity over the direct implementation. Moreover, we present a simple approach for the construction of CMOSTflip-flop by modification of clock signal ofDflip-flop, which is found to be more efficient than theTflip-flop derived fromJKflip-flop. The extended sequential logic is used for the implementation of finite-field multiplication overGF(2m) and carry-save addition of real numbers. In both these cases, the use of extended logic is found to offer a substantial saving in area and time complexity over the conventional implementations.