An FFT processor based on the SIC architecture with asynchronous PE
J. Melander, T. Widhe, Kent Palmkvist, Mark Vesterbacka, Lars Wanhammar · 2002
A SIC architecture with asynchronous bit-serial PEs is presented and applied to the Sande-Tukey's FFT. The resulting architecture can easily be modified for higher throughput and/or lower power consumption. Using this architecture a high-performance chip for use in an OFDM transmission system has been designed.