A field programmable gate array chip with hierarchical interconnection structure
Yen‐Tai Lai, Chi‐Chou Kao, Tsun-Cheng Chang, Kun-Nern Chen · 2002
This paper presents the architecture and implementation of a field programmable gate array chip with hierarchical interconnection structure. The new field programmable gate array has higher performance than conventional field programmable gate arrays. Its advantages are high density, fast speed, and the flexibility to fit designs into the architecture quickly. The schematic circuit of the FPGA is described, and its layout by using full-custom top-down method is presented.