A VLSI array processor with embedded scalability for hierarchical image compression
Javier Vega-Pineda, M.A. Suriano, V.M. Villalva, Sergio D. Cabrera, Yi-Chieh Chang · 1996
In this article we present a VLSI implementation of the wavelet based High-Speed Pyramid (HSP) transform algorithm which can be used for lossy hierarchical image coding. The HSP chip features include computation of the forward or inverse HSP transform, user selectable level dependent quantization, generation of zerotree flag bits and testability circuitry. The symmetrical chip structure permits the 5 by 5 pixel array size to be enlarged to 9 by 9 by connecting four chips together. In this way a larger block of image pixels can be processed at the same speed. Details of the general chip design, the replicated cell, additional circuitry and performance estimates are discussed.