SAD-Based Stereo Matching Circuit for FPGAs
Stefania Perri, Daniela Colonna, Paolo Zicari, Pasquale Corsonello · 2006
This paper presents a novel FPGA-based stereo matching system. The proposed circuit operates on 512times512 stereo images with a maximum disparity of 255. It achieves a 286 MHz running frequency and a frame rate of 25.6 f/s.