High performance real-time neural scheduler for ATM switches
J.M. Pousada-Carballo, Francisco Javier González-Castaño, Pedro S. Rodríguez‐Hernández, Ubaldo M. García‐Palomares · IEEE Communications Letters · 2000
Input-buffered asynchronous transfer mode (ATM) packet switches are simpler than output-buffered switches. However, due to HOL blocking, their throughput is poor. Neural schedulers represent a promising solution for high throughput input-buffered switching, but their response time variance is too high for realistic hard real-time constraints. To overcome this problem, we formulate and evaluate a new neural scheduler with bounded response time.