Digital hardware implementation of bus-based, field-ordered Hopfield network using VHDL
Kuek Chian Shiun, Wan Ahmad Tajuddin Wan Abdullah, Burhanuddin Kamaluddin · 2004
This paper presents some new approach in designing hardware discrete Hopfield network. For the network architecture, the bus-based approach is used to largely reduce the number of connection count. Field-ordered updating algorithm is used in place of the typical random-ordered updating due to its added advantage in finding global minimum. As for the implementation, VLSI language has been used due to its ease in describing and documenting complex digital design. Besides, modern CAD tools enables the synthesis of VHDL codes into layout plans on customized FPGA chips and making corresponding timing simulation.