Hardware modifications in radix-2 cascade FFT processors
J.P. Agrawal, J. Ninan · IEEE Transactions on Acoustics Speech and Signal Processing · 1978
In this correspondence, some techniques are presented, which reduce coefficient storage and hardware cost of cascade FFT processors. Computer simulation results are presented which give hardware-error tradeoffs and also show the effect of coefficient accuracy. A reduced hardware multiplier is suggested which gives only insignificant loss in accuracy.