CRIS: a test cultivation program for sequential VLSI circuits
Daniel G. Saab, Youssef G. Saab, Jacob A. Abraham · International Conference on Computer Aided Design · 1992
This paper discusses a novel approach to cultivating a test for combinational and sequential VLSI circuits described hierarchically at the transistor, gate, and higher levels. The approach is based on continuous mutation of a given input sequence and on analyzing the mutated vectors for selecting the test set. The approach uses hierarchical simulation technique in the analysis to drastically reduce the memory requirement, thus allowing the test generation for large VLSI circuits. The algorithms are at the switch level so that general MOS digital designs can be handed, and both stuck-at and transistor faults are handle accurately. The approach has been implemented in a hierarchical test generation system, CRIS, that runs under UNM on SPARC workstations. CRIS has been used successfully to generate tests with high fault coverage for large combinational and sequential circuits.