A low-power DSP core architecture for low bitrate speech codec
Hiroyuki Okuhata, Morgan Hirosuke Miki, Takao Onoye, Isao Shirakawa · 2002
A VLSI implementation of a low-power DSP is described, which is dedicated to the G.723.1 low bitrate speech codec. A number of sophisticated DSP microarchitectures are devised mainly on dual multiply accumulators, rounding and saturation mechanisms, and two-banked on-chip memory. The proposed DSP architecture has been integrated in a total area of 7.75 mm/sup 2/ by using a 0.35 /spl mu/m CMOS technology, which can operate at 10 MHz with the dissipation of 45 mW from a single 3 V supply.