Communication Centric Architectures for Turbo-Decoding on Embedded Multiprocessors
Frank Gilbert, Michael J. Thul, Norbert Wehn · 2003
Software implementations of channel decoding algo-rithms are attractive for communication systems with their large variety of existing and emerging standards due to their flexibility and extensibility. For high throughput, however, a single processor can not provide the necessary compute power. Using several processors in parallel without exploit-ing the internal parallelism of the algorithm leads to intol-erable overhead in area, power consumption, and latency. We propose a multiprocessor based Turbo-Decoder im-plementation where inherently parallel decoding tasks are mapped onto individual processing nodes. The implied challenging inter-processor communication is efficiently handled by our framework such that throughput is not de-graded. In this paper we present communication centric architectures from buses to heterogenous networks that al-low to interconnect numerous processors to perform high throughput Turbo-decoding. 1