Parallel evaluation of a parallel architecture by means of calibrated emulation
Henk Muller, Paul W. A. Stallard, David H D Warren, S Raina · 2002
A parallel transputer-based emulator has been developed to evaluate the Data Diffusion Machine (DDM)/spl minus/a highly parallel virtual shared memory architecture. The emulator provides performance results of a hardware implementation of the DDM using a calibrated virtual clock. Unlike the virtual clock of a simulator, the emulator clock is bound to a fixed fraction of real time, so individual processors may time actions independently without the need for a global clock value. Each component of the emulator is artificially slowed down, so that the balance of the speeds of all components reflects the balance of the expected hardware implementation. The calibrated emulator runs an order of magnitude faster than a simulator (the application program is executed directly and there is no overhead for the maintenance of event lists) and, more importantly, the emulator is inherently parallel. This results in a peak emulation speed of 27 MIPS when simulating a machine with 81 leaf nodes on a 121-node transputer system.>