A single board test system: changing the test paradigm
Garry Gillette · 2002
There are three areas in which to drive down the cost of test: reducing long term ownership cost, reducing test and programming time, and reducing initial capital cost. To address all three areas simultaneously in a test system requires challenging the current tester paradigm. This paper will describe such a shift obtained by aggressive integration of a test system on a single printed circuit board without compromising test functionality. The issue is analogous to that posed by the latest Pentium laptop when compared to a mainframe computer. To achieve this level of integration the test system design uses 3.3 V 0.5 micron CMOS ULSI ASIC technology, CMOS custom analog technology, and Complementary Bipolar technology for high speed pin electronics. It is self-contained on a single printed circuit board of 150 square inches in area. The result is an order of magnitude reduction in initial capital cost with a significant increase in test functionality. A concurrent reduction in the physical resources needed to support and interface the test system results in further cost reductions, and the uncompromised test system feature set allows test and programming overhead time to be reduced to a minimum. In addition, previously very expensive capabilities, such as combined memory and logic test, common I/O pins, tester-per-DUT architecture, total programming agility and elimination of relays are achieved.