Synthesis of interface controllers from timing diagram specifications
A. El-Aboudi, E.M. Aboulhamid, E. Cerny · 2002
We present a method for verifying the realizability of a timing diagram, ensuring the synthesis of the underlying interface is possible. If necessary, a heuristic is introduced to render explicit hidden timing constraints implied by the specification. A relative schedule of output events is computed, accepting input events from the complete timing space defined by the assumed constraints on the environment.