Efficient hardware-software co-design for the G.723.1 algorithm targeted at VoIP applications
Shridhar Mubaraq Mishra, Ambily Balaram · 2002
With the growing demand for Voice over Internet Protocol (VoIP) services, it has become increasingly important to design ASICs implementing the H.323 algorithm efficiently, with capabilities of handling multiple channels, so as to allow cost-effective implementation of H.323 GSTN and ISDN gateways. In this paper, the G.723.1 speech codec, which is an integral part of the H.323 specification, is investigated and an efficient hardware-software co-design is proposed. This design reduces the MIPS requirement for the G.723.1 implemented on the 16 bit OAK DSP core by 17% for the 5.3 kbits/s encoder and by 11% for the 6.3 kbits/s encoder. This is achieved by identifying the inherent parallelism in the G.723.1 algorithm and implementing a sizeable portion of the algorithm in hardware, while the DSP is concurrently executing part of the algorithm. The overhead of transferring data between the firmware and hardware is reduced by using efficient memory access structures.