Design and Hardware Construction of a High Speed and Memory Efficient Huffman Decoding
Reza Hashemian · 1994
Hardware design of a high speed and memory efficient Huffman decoder, introduced in(l), is presented. The algorithm developed is based on a specific Huffman tree structure using a code-bit clustering scheme. The method is shown to be extremely efficient in memory requirement, and fast in searching for symbols. For an experimental video data with code-words extended up to 13 bits, the entire memory space needed is shown to be 122 words in size, compared with normally 213 = 8196 words memory space re- quirement. The design of the decoder is carried out using silicon- gate CMOS process.