Efficient time-space mappings of nested loops onto multidimensional systolic arrays with a flexible buffer scheme
R. Varadarajan, Francis P. Augustine · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 1993
The task of mapping a nested loop algorithm onto a multidimensional systolic array is considered. A buffer structure for the processing elements (PEs) that allows the data tokens to arrive at the PE earlier than when they are needed is proposed. Necessary and sufficient conditions for valid mappings using this buffer structure are then given. A refinement technique for deriving efficient statement level mappings from iteration level mappings is then proposed.>