High Speed Word-parallel Bit-Serial Normal Basis Finite Field Multiplier and Its FPGA Implementation
Ashkan Hosseinzadeh Namin, Huapeng Wu, Majid Ahmadi · 2006
A new high speed word-parallel bit-serial finite field multiplier using a reordered normal basis is presented. The proposed multiplier is used for a class of finite fields in which there exists a type II optimal normal basis. FPGA implementation of the proposed multiplier with other similar multipliers are also presented. Architectural analysis and the FPGA simulation results show that the proposed multiplier is faster compared to the previous similar proposals. I. INTRODUCTION