Cell processing LSIs for 2.4 Gbit/s SDH-based ATM transmission system
Hideo Tatsuno, Nobuyuki Tokura, Yoshihiro Maeda, Kazuro Kikuchi · Electronics Letters · 1991
This Letter introduces cell processing large-scale integrated circuits (LSIs) suitable for byte-oriented systems operating at 2.4 Gbit/g. The LSIs are based on a newly proposed cell delineation circuit which uses a pipeline processing technology to realise byte-by-byte shift operations, an error-detect and error-correct circuit and a descrambling circuit. Prototype LSIs, constructed with a super-selfaligned process technology (SST), are tested at up to 3.7 Gbit/s.