250-600 MHz 12b digital filters in 0.8-0.25 /spl mu/m bulk and SOI CMOS technologies
Lars E. Thon, G.P. Coleman, Werner Rausch, Dominic J. Schepis, Reinhard Schulz, F. Assadaraghi, GHAVAM G. SHAHIDI, D.D. Tang · International Symposium on Low Power Electronics and Design · 1996
This paper describes a family of high-speed Finite Impulse Response (FIR) digital filters that have been scaled across three generations of CMOS processes. The processes include commercial varieties as well as experimental bulk and low power Silicon-On-Insulator (SOI) technologies. Wafer tests demonstrate the speed and power advantages of the experimental SOI technology when applied to a 24 k-device digital signal processing (DSP) function, by direct comparison with the same filter manufactured in conventional (bulk) CMOS. The filters presented here have 8 taps and operate on 6 b data with 6 b programmable coefficients and deliver 12 b fixed-point output values, but the layout design is modular so that the number of taps and bits can be changed easily. The filters operate with maximal speeds of 250-600 MHz depending on the fabrication technology, and are suitable for the equalization task in Partial Response magnetic recording channels.