A 2 V CMOS programmable pipelined digital differential matched filter for DS-CDMA system
She-Hwa Yen, Chorng‐Kuang Wang · AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360) · 2003
This paper presents a 2 V DS-CDMA programmable digital matched filter with a differential and pipelined structure. A differential PN (Pseudo-Noise) code scheme is adopted to reduce the number of multiplication and summations (M&S). The PDDMF (Pipelined Digital Differential Matched Filter) not only saves hardware and power, but also improves the operation speed, which makes PDDMF more suitable for personal communication at high speed and low power requirements than the conventional approach. The PDDMF, implemented in a 0.6 /spl mu/m CMOS technology, is clocked at 2.5 MHz and consumes 1.6 mW from a single 2 V power supply.