Symbolic oriented stuck fault modeling of CMOS sequential circuits
Predrag M. Petković, D. Milovanovic, Vladimir D. Živković · 2002
This paper presents a new method for stuck fault modeling of CMOS sequential circuits at transistor level. The method is based on the application of Transistor Logic Conductance Functions (TLCF) which are obtained using symbolic simulation. Multiple faults can also be modeled with our approach. Finally, the application of the TLCF for test pattern generation is included.