Hardware implementations of the SHA-3 candidates Shabal and CubeHash
Markus Bernet, Luca Henzen, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner · 2009
At the current stage of the SHA-3 competition organized by the U.S. National Institute of Standards and Technology (NIST), the 51 accepted candidates for the next-generation cryptographic hash standard SHA-3 are being evaluated in terms of security properties, computational efficiency, and memory requirements. While detailed information about the software performance on various platforms is provided for all candidates, a thorough analysis of the algorithm performance on dedicated hardware is often missing. Nevertheless, hardware efficiency is of substantial importance, as SHA-3 is expected to be implemented in many resource-constrained applications. This work intends to complement the specifications of the candidates Shabal and CubeHash by investigating their suitability for both high-speed and low-area VLSI implementations. Shabal's high speed core reaches a fairly large throughput of 6.351 Gbps at a complexity of 41.32 k gate equivalents (GE), whereas CubeHash makes do with a complexity of only 7.63 kGE and is thus particularly appealing for lightweight implementations.