Behavioral fault simulation in VHDL
P. C. Ward, James R. Armstrong · 1990
This paper presents two tools which facilitate the fault simulation of behavioral models described using VHDL. The first tool is the Behavioral Fault Mapper (BFM). The BFM algorithm accepts a fault-free VHDL model and a fault list of N faults from which it produces N faulty models. The process of mapping the faults in the fault list onto copies of the original VHDL model is automated. The N faulty models are immediately suitable for fault simulation. The second tool presented is the Test Bench Generator (TBG). The TBG algorithm creates the VHDL TestBench and all other files necessary to complete a batch-mode fault simulation of the N faulty models.