An Accumulator—Based Test-Per-Clock Scheme
D. Magos, Ioannis Voyiatzis, Steffen Tarnick · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2010
We propose a new scheme for reducing the test application time in accumulator-based test-pattern generation. Within this framework, we reduce the problem of efficiently generating test-patterns to that of finding the shortest Hamiltonian path in an associated directed graph. The resulting scheme exhibits extremely low demand for hardware based on a combination of decoders whose inputs are driven by a very slow external tester. Experimental results on ISCAS benchmarks substantiate the superiority of the proposed scheme over the previously-published test-set embedding approaches for accumulator-based test generation.