Learning algorithms for a neural network in FPGA
T. Aoyama, Qianyi Wang, Ryosuke Suematsu, Ryōsuke Shimizu, Umpei Nagashima · 2003
We researched simplified multi-layer neural networks to equip them in one-chip FPGA. We reexamined neuron functions, bits number of connection-weights, and learning methods; and proposed a "and/or"-neural network, which is derived from the disjunctive-normal-form in the binary logic; however it can be expanded to the multi-valued. We designed the network by using HDL.