FPGA Prototyping Strategy for a H.264/AVC Video Decoder
Vagner Rosa, Wagston Tassoni Staehler, Arnaldo Azevedo, Bruno Zatt, Roger Porto, Luciano Volcan Agostini, Sérgio Bampi, Altamiro Susin · Proceedings · 2007
This paper presents the prototyping strategy used to validate the designed modules of a main profile H.264/AVC video decoder designed to achieve 1080p HDTV resolution, implemented in a FPGA. All modules designed were completely described in VHDL and further validated through simulations. The post place-and-route synthesis results indicate that the designed architectures are able to target real time when processing HDTV 1080p frames (1080times1920). The architectures were prototyped using a Digilent XUP V2P board, containing a Virtex-II Pro XC2VP30 Xilinx FPGA. The prototyping strategy used an embedded Power PC and associated logic and buffering to control the modules under prototyping. A host computer, running the reference software, was used to generate the input stimuli and to compare the results, through a RS-232 serial interface.