Testability measures reduce test generation time in sequential ATPG
Enrico Macii, Angelo Raffaele Meo · 2003
A technique for estimating the testability of the nodes of a sequential circuit, whose description can be either at the gate-level or at the block-level, is described. Two weight functions are evaluated for each node of the network, and the results obtained are used in an existing set of automatic test pattern generation (ATPG) procedures in order to reduce the test generation time. Experimental results obtained on the ISCAS '89 standard set of benchmark circuits show the effectiveness of the method.>