An adaptive system-on-chip for network applications
Roman Koch, Thilo Pionteck, Carsten Albrecht, Erik Maehle · 2006
This paper presents the hardware architecture of Dy-naCORE, a dynamically reconfigurable system-on-chip for network applications. DynaCORE is an application specific coprocessor for offloading computationally in-tensive tasks from a network processor. The system-on-chip architecture is based on an adaptable network-on-chip which allows the dynamic replacement of hardware modules as well as the adaptation of the on-chip com-munication structure. The coprocessor leverages the active partial reconfiguration feature of modern FPGAs in order to adapt to shifting demand patterns. An em-bedded general-purpose processor core within the copro-cessor runs software which manages the configurations of the device. With reference to a prototypical imple-mentation targeting a Xilinx Virtex-II Pro FPGA, this paper focuses on on-chip communication issues. Top-ics include the integration of PowerPC processor cores into the configurable logic as well as the mode of oper-ation of the network-on-chip. 1.