A battery backup 64K CMOS RAM with double-level aluminum technology
T. Watanabe, M. Hayasi, Ikue Sasaki, Yasuo Akatsuka, Tohru Tsujide, Hirohiko YAMAMOTO, Osamu Kudoh, S. Takahashi, Takahiko Hara · IEEE Journal of Solid-State Circuits · 1983
A full CMOS 8K /spl times/ 8 bit RAM has been developed, incorporating a new circuit to transfer the memory automatically to the data-retention mode when supply voltage is lowered. For reducing operating power dissipation, internally synchronous circuits and a split power control technique were employed. A minimum cell size was obtained through the use of a double-level aluminum process.