BATMAN: a new architectural design of a very large next generation gigabit switch
Muh-rong Yang, Gin-Kou Ma · 2002
In spite of the recent advances of technology, the limitation on the switching size is the primary implementation constraint. Practical dimensions are limited to the small size of a module. To build a larger dimension, more than one module is interconnected in a multistage configuration. Moreover, internal switching fabrics of these interconnected modules are usually speed-up to a higher data rate in order to reduce excessive queuing delay. In this paper, a new architectural design of a very large next generation gigabit switch, called BATMAN (Banyan ATM Architectural Network), is introduced. The proposed switch has the structure of an N/spl times/N Banyan network, and recursively followed by 2/sup k/ groups of shared buffers, and N/2k 2/sup k//spl times/2/sub k/ Banyan networks, where k is incremented from 1 to [log/sub 2/N/log/sub 2//sup /spl rho//], and /spl rho/ is the speed-up factor. In its simplest form, it has the structure of an N/spl times/N Banyan network, N/4 groups of shared buffers, and N/4 4/spl times/4 Banyan routing networks. In each Banyan network module, universal packet timeslot (UPTS) is adopted. Because the hardware complexity of the proposed switch architecture is low, the architecture allows for the modular growth of its size from small to very large dimensions without sacrificing its overall delay/throughput performance.