Development of a digital FPLL ASIC for GA HDTV receivers
Dong-Seog Han, Myeong-Hwan Lee, Kil-Houm Park · IEEE Transactions on Consumer Electronics · 1997
We propose a new digital carrier recovery loop architecture for the Grand Alliance high definition television (HDTV) system. We have developed an application specific integrated circuit (ASIC) based on the new architecture. The developed ASIC has a gate count of 60 K with a gate array technology that features 0.5 /spl mu/m, 3.3 V and 2-metal-layer technology. The pull-in range of the proposed architecture is about /spl plusmn/250 kHz with 0 dB carrier-to-noise ratio (CNR).