An efficient scheduling algorithm for combined input-crosspoint-queued (CICQ) switches
Xiao Zhang, Laxmi Narayan Bhuyan · 2005
With today's ASIC technology, a large amount of memory can be easily implemented in a single chip. This makes the combined input-crosspoint-queued (CICQ) crossbar switch a more attractive solution than the traditional input-queued (IQ) crossbar switch because of the simplicity of the CICQ switch scheduling. We propose a shortest crosspoint buffer first (SCBF) scheme, and prove that it achieves 100% throughput for any admissible traffic. To facilitate hardware implementation, a maximal SCBF solution is also proposed. Our simulations show that the maximal SCBF performs almost identically to the maximum solution, and better than existing IQ and CICQ schemes. The time complexity of the maximal SCBF is O(log N), feasible for fast hardware implementation.