Correlation-reduced scan-path design to improve delay fault coverage
Weiwei Mao, Michael D. Ciletti · 1991
Experimentaldata is presented for eleven benchmark circuits to show how test pattern correlation in a scan-path design circuit adversely affects delay fault coverage, and to demonstrate that most undetected &lay faults caused by the test pattern correlation are close to latch outputs.Topology-based latch correlation measures are introduced and used by a companion latch arrangement algorithm to guide the placement of latches in a scan-path &sig~with the objective of minimizing the effect of the test pattern comelation and maximizing the delay fault coverage.Experimental results with benchmark circuits indicate that the scan-path found by the algorithm clearly achieves better delay fault coverage than a scan-path having no deliberate arrartgemeng and, in fac~achieves nearly the coverage that can be gotten by unrestricted application of the test vectors to the circuit without a scars-path.The data also indicates that the algorithm is most effective in covering delay faults that are located nearest the latch outputs of the circuit.The approach has an advantage over other arrangement schemes in that it is simple to implement and does not require significant computational time even for large circuits.