Frame-level pipelined motion estimation array processor
Surin Kittitornkun, Yu Hen Hu · IEEE Transactions on Circuits and Systems for Video Technology · 2001
A systolic motion estimation processor (MEP) core architecture implementing the full-search block-matching (FSBM) algorithm is presented. A unique feature of this MEP architecture is its support of frame-level pipelined operation. As such, it is possible to process pixels from consecutive frames without any processor idle time. It is designed so that no data broadcasting operations are required, and achieves 100% fully pipelined computation. It compares favorably with existing MEP architectures in terms of both performance and complexity of architecture.